In this way, the elements of an extension field fit exactly in one storage unit and can be efficiently manipulated in software. Particularly good choices for such fields are the extension Galois fields GF ( 2 n ), defined as extensions of GF ( 2 ), where n is related to the size of the registers in the underlying processor (usually words of 16 or 32 bits). This strategy makes use of other finite fields more suited for current processors. On the other hand, the second approach consists of adopting a new design, known as word-oriented LFSR. Although the existence of techniques, such as circular buffer or sliding windows, the effects are believed to be less significant than the ones obtained with the second approach. On the one hand, improving performance by optimizing the implementation of original bit-oriented LFSRs. In order to solve these problems, there are two different strategies. Secondly, binary LFSR provide only one output bit per clock pulse, which makes the software implementations very inefficient and involves a clear waste of modern processors capabilities. If the length of LFSRs exceeds the processors word size, these operations will be specially time-consuming. First, in order to update the state of a LFSR, a processor has to spend many clock cycles to perform the registers shifting or output generation operations. This approach is appropriate for hardware implementations, but its software efficiency is low because of two important drawbacks. LFSR have been traditionally designed to operate over the binary Galois field GF ( 2 ). Linear feedback shift registers (LFSR) have been widely used as sequence generators in many different areas: computer communications, digital TV broadcasting, global positioning systems (GPS), built-in self test of integrated circuits, error correcting codes and as building blocks in stream ciphers (e.g.
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